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SYSTEMVERILOGSHA256

SYSTEMVERILOGSHA256 is an open-source Verilog/SystemVerilog hardware design containing a parameterized SHA-256 calculator and a Bitcoin block-header miner module. Its included testbenches support simulation with Icarus Verilog.

Explore the practical guide ↓

Independent OpenViST project profile, based on linked sources.

SYSTEMVERILOGSHA256 — OpenViST project profile in Mining.
OpenViST project illustration. See the linked sources for product details.
Understand the project

Practical overview

When it fits

Use it when you want source-level material for a Verilog SHA-256 design or a documented Icarus Verilog simulation of Bitcoin block-header hashing.

Who it is for

  • FPGA and digital-logic developers studying or adapting SHA-256 hardware.
  • Bitcoin developers who want to simulate block-header hashing.
  • Learners using Verilog testbenches to inspect hash results.

Documented uses

  • Hash data with the parameterized SHA-256 calculator.
  • Calculate a Bitcoin block-header hash with the miner module.
  • Simulate a block-header hash and inspect the command-line result.
Before you choose

Requirements & limits

The repository is public, open source, and licensed under GPL-3.0.

  • Icarus Verilog is the documented simulator; the README notes the modules are converted to Verilog because it does not natively support SystemVerilog.
  • The miner testbench expects an 80-byte block header and reports the calculated result in the command line.
  • The README lists FPGA execution as unfinished, distinguishing the documented simulation use from hardware deployment.

Check current requirements in the official documentation. Source-based guidance does not mean OpenViST has run or independently tested this project.

Source-based practical guide

Simulate a Bitcoin block-header hash

Use the included miner testbench to calculate an 80-byte Bitcoin header hash in Icarus Verilog.

Before you start

  • The repository’s miner module and miner_tb.sv testbench
  • Icarus Verilog
  • An 80-byte Bitcoin block header

Steps

  1. Put the 80-byte block header in the testbench’s message register.

  2. Run the miner_tb.sv simulation with Icarus Verilog.

  3. Read the computed result output in the command line.

Expected outcome

The simulation prints the calculated block-header hash.

Guide limitations

  • The documented procedure covers simulation, not execution on FPGA.
  • The README notes that the modules are converted to Verilog for Icarus Verilog.
Documentation 1 ↗
Evidence and transparency

Sources & review

Official repository ↗
Source record details
Source availability
Active
Sources checked
17 October 2026
Original website title
unixb0y/SystemVerilogSHA256 · Official homepage title · retained in its source language
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